This invention relates generally to high frequency power semiconductor device processing, and more specifically to methods for making vertical compound semiconductor field effect transistor (FET) devices.
In the area of computer and peripheral power supply applications, there are several factors driving future performance and demand. Such factors include an increase in output power requirements because of higher microprocessor speeds, smaller system size (i.e., reduced circuit board space), lower cost, improved transient response, and lower output voltage ripple (i.e., lower microprocessor operating voltages). Additionally, advancing microprocessor needs, which include decreasing operating voltage and increasing current requirements, will require power conversion devices and circuits that enable highly efficient and tightly regulated power. These devices and circuits must operate at higher frequencies and exhibit enhanced thermal characteristics.
Most losses in high frequency switching power circuits are determined by the physical properties of semiconductor devices, such as diodes, FETs, and insulated gate bipolar transistors. Although silicon based MOSFET devices are a primary choice for many power conversion applications, they have inherent limitations for high frequency applications due to their physical structure. Such limitations include high reverse recovery charge, high gate charge, gate resistance, and high on resistance, which detrimentally impact power dissipation and thermal response characteristics.
Unlike silicon, GaAs is a direct bandgap compound semiconductor material with an inherent property of high electron mobility (8500 cm2/V-sec), which is greater than 4× that of silicon (1500 cm2/V-sec). Also, GaAs has a larger bandgap of 1.42 eV compared to 1.1 eV for silicon, which provides, among other things, enhanced performance at elevated temperatures. Additionally, the reverse recovery charge of a GaAs FET device is approximately 100× lower than that of a silicon FET device. These properties make it an ideal candidate for high frequency applications as well as applications where thermal response characteristics are important.
Several vertical compound semiconductor FET devices have been reported. For example, U.S. Pat. Nos. 5,231,037 and 5,610,085 by H. T. Yuan et al. and assigned to Texas Instruments, Inc., both show vertical FET devices having a buried p-type gate structure covered by an n-type epitaxial overgrowth layer. One problem with the Yuan devices is that defects can be introduced in the epitaxial overgrowth layer during epitaxial growth, which results in a FET device having high leakage currents and low blocking gain. Additionally, the '037 and '085 structures are costly to manufacture.
In U.S. Pat. No. 4,262,296 by Shealy et al. and assigned to General Electric Company, a trapezoidal groove Schottky metal gate vertical FET is described. The Shealy design has several problems including high leakage caused by the Schottky gate, which results in low blocking gain. Additionally, a complementary etch profile in the orthogonal crystal directions lowers blocking gain as well.
In European Patent Application EP0874394, a method for making vertical FET is disclosed. In '394, the gate region is located at the bottom of a single etched trench. One problem with the '394 method is that it places the gate region in poor proximity to the channel, and the gate region has limited extension along the channel. These shortcomings result in a FET device with low blocking gain.
Accordingly, a need exists for a method of manufacturing vertical FET devices that have improved blocking gain, lower gate capacitance, and lower on resistance. Additionally, it would be beneficial for the method to support high volume manufacturing and to be cost effective.